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Image / Intel 1103 Memory chip package, 1970

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Title
Intel 1103 Memory chip package, 1970
Creator
Intel Corporation
Contributor
Intel Memory Packages
Date Created and/or Issued
1970 1970
Publication Information
Intel Museum Archives
Contributing Institution
Intel Museum
Collection
Intel Museum Silicon Valley History Online Collection
Rights Information
Copyright ©Intel Corporation 1970. All Rights Reserved. Transmission and reproduction of a single copy of this work for non-commercial use in research or teaching in the United States is permitted if Intel is credited as the source of the work. The work must remain intact, as a complete whole and may not be combined with any other image or work to create a new document. Copyright ©Intel Corporation 1970. All Rights Reserved. Transmission and reproduction of a single copy of this work for non-commercial use in research or teaching in the United States is permitted if Intel is credited as the source of the work. The work must remain intact, as a complete whole and may not be combined with any other image or work to create a new document.
Description
Color slide of the Intel 1103 Memory chip package. Concept: Ted Hoff. Design: John Reed. This first DRAM is also the first of the chips that would enable the explosive growth of PC's; 1970 MIL became the official second source supplier for Intels 1103; MIL deviated from Intels specification to increase the yield by means of reducing the chip area and enlarging the wafers but the yield decreased to almost zero. Intel stepped into the breach and satisfied nearly the whole market need for 1103; in the end of 1971 Intel delivered the 1103 to 14 of the 18 leading computer manufacturers. Since the production costs of the 1103 were much lower than the costs of a core memory or a 1101 the 1103 could establish within the market rapidly, became the world's best selling memory chip and was finally responsible for the obsolescence of magnetic core memory. Technology: The 1103 is a 1K bit PMOS Dynamic Random Access Memory (DRAM) chip; refreshing of all 1024 bits is accomplished in 32 read cycles and is required every two milliseconds.
Type
image
Format
24 x 16 cm.
Identifier
http://ark.cdlib.org/ark:/13030/kt0c6016vq
cstcli 1998. 7 RNB Slide 17-5-1
Language
English
Subject
Electronic industries; Memory chip packages; Photographs; Santa Clara (Calif.); Santa Clara County (Calif.)--History; Semiconductor wafers; Technology
Source
lcsh, local

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